1. Field of the Invention
The present invention relates generally to analog circuitry and, in particular, to band gap circuitry used to generate reference voltages having a controllable temperature coefficient.
2. Description of Related Art
In analog and mixed signal circuits, a reference voltage is sometimes needed that does not vary over temperature or that varies in a predetermined way over temperature. Typical of such circuits is a circuit commonly referred to as a band gap voltage reference circuit. A band gap circuit relies upon a difference in base-emitter voltage of two bipolar transistors, with such difference voltage having a positive temperature coefficient. That difference voltage, or a voltage derived from the difference voltage, is combined with another voltage, typically a base-emitter voltage, having a negative temperature coefficient, to produce a reference voltage. In most cases, the voltages are combined so that the reference voltage has a zero temperature coefficient, but the reference voltage can also have a controlled positive or controlled negative temperature coefficient if desired. Regardless of the temperature coefficient of the reference voltage, such circuits are referred to herein as band gap circuits or band gap reference circuits.
In a CMOS process, the only bipolar transistors available are parasitic vertical PNP transistors having their respective collectors formed in a common P type substrate. This places limits of the implementation of circuits using those transistors. Various CMOS band gap voltage reference circuits have been developed, many of which have limitations on the minimum supply voltage.
Referring to the drawings, FIG. 1 is a diagram of one such prior art band gap reference circuit. A pair of parasitic vertical PNP transistors 8A and 8B are included which are diode-connected with the base and collectors of each transistor being connected to the circuit common. Transistor 8B is implemented having an emitter area which is twenty-four times (24xc3x97) as large as the emitter area of transistor 8A (1xc3x97). The emitters of transistors 8A and 8B are respectively connected to the drains of a pair of similar P type MOS transistors 6A and 6B. Transistor 8B is connected to MOS transistor 6B by way of a resistor R1.
A third P type MOS transistor 6C, having a gate connected in common with the gates of transistors 6A and 6B, is connected to an emitter of a third parasitic vertical PNP transistor 10 by way of a resistor R2. All three MOS transistors 6A, 6B and 6C have their sources connected in common to the supply voltage. PNP transistor 10 has the same emitter area (1xc3x97) as transistor 8B and is also connected as a diode, with base and collector connected to the circuit common. An operational amplifier 12, which functions as an error amplifier, has an output connected to the common gates of transistors 6A, 6B and 6C, an inverting input connected to a node A intermediate transistors 6A and 8A and a non-inverting input connected to a node B intermediate resistor R1 and transistor 6B.
In operation, amplifier 12 controls the gate-source voltage of transistors 6A, 6B and 6C such that the voltages at nodes A and B are equal, ignoring the small input offset voltage of the amplifier. Transistors 6A and 6B are the same size and have the same gate-source voltage so that both transistors will conduct approximately the same current Ith. Transistors 8A and 8B will also conduct the same current, Ith, with transistor 8A operating at twenty-four times the current density given that the emitter area of the transistor only 1xc3x97 compared to the 24xc3x97 of transistor 8B. As is well known, transistors 8A and 8B will operate at different base-emitter voltages (xcex94Vbe) with such difference voltage being relatively independent of the absolute magnitude of the current. The equation for xcex94Vbe is as follows, with Ja and Jb representing the current density of transistors 8A and 8B, respectively:                               Δ          ⁢                      xe2x80x83                    ⁢          Vbe                =                  Vt          ⁢                      xe2x80x83                    ⁢          ln          ⁢                      xe2x80x83                    ⁢                      Ja            Jb                                              (        1        )            
Vt is the thermal voltage (kT/q). Assuming that transistors 8A and 8B conduct the same current Ith, the ratio of current density is determined solely by the {fraction (1/24)} ratio of emitter areas, resulting in xcex94Vbe of 80 millivolts. Thus, assuming that the Vbe of transistor 8A is, for example, 650 millivolts, the Vbe of transistor 8B will be 80 millivolts less or 570 millivolts at room temperature. Since the voltages at nodes A and B are equal, the xcex94Vbe voltage of 80 millivolts will be dropped across resistor R1. In a typical application, resistor R1 will be set to about 160 kohms thereby setting current Ith to 500 nanoamperes (80 millivolts/160 kohms). As can be seen in equation (1), voltage xcex94Vbe has a positive temperature coefficient since Vt has a positive temperature coefficient of +0.085 millivolts/xc2x0 C. Thus, current Ith will also have a positive temperature coefficient.
The band gap output voltage Vbg is the sum of the base-emitter voltage of transistor 10, voltage Vbe(10), and the voltage drop across resistor R2, voltage V(R2). Since the base-emitter voltage Vbe(10), typically 650 (millivolts), has a negative temperature coefficient (xe2x88x922 millivolts/xc2x0 C.), the value of resistor R2 is selected so that a positive temperature coefficient voltage V(R2) is produced having a magnitude sufficient to offset the negative temperature coefficient of voltage Vbe(10). Setting resistor R2 to 1.2 Meg ohms will produce a voltage V(R2) of about 600 millivolts. This will produce a band gap output voltage Vbg of 1.25 volts having the desired first order zero temperature coefficient.
One of the limitations of the FIG. 1 prior art circuit relates to the implementation of the operational amplifier 12. FIG. 2A is a simplified diagram of the input stage of an amplifier utilizing N type MOS devices and FIG. 2B is a diagram of an input stage utilizing P type devices. Referring first to FIG. 2A, input V+, the gate of transistor 16A, is connected to node A of FIG. 1 and input Vxe2x88x92, the gate of transistor 16B, is connected to node B. As previously noted, both nodes A and B are at 650 millivolts, the base-emitter voltage of transistor 8A.
In order for the FIG. 2A amplifier to operate properly, inspection of the input indicates that the voltage at the inputs, the common mode input voltage, must be at least as large as the sum of the gate-source voltage Vgsn of N type transistor 16A and voltage Vdsatn of tail current source N type transistor. Voltage Vdsatn is the minimum drain-source voltage necessary for transistor 18 to operate in the saturation region where the transistor functions as a current source. The gate-source voltage Vgsn is equal to Vdsatn+Vtn where Vtn is the threshold voltage of the N type transistors. Assuming that Vtn is 700 millivolts and Vdsatn is 200 millivolts, it can be seen that the FIG. 2A amplifier requires a minimum common mode input voltage of 1.1 volts, well above the actual voltage of 650 millivolts at the amplifier inputs. This presents a problem.
One solution to the above noted problem is to use MOSfet having a reduced threshold voltage, usually in the range of 200 millivolts. However, such devices are typically not available on standard CMOS processes. Another approach is to use an input stage having P type devices as shown in FIG. 2B. Inspection of the FIG. 2B circuit shows that the supply voltage must be at least equal to the sum of the voltage applied to the gates of input transistors 22A and 22B, the voltage at nodes A and B, plus the sum of the gate-source voltage Vgsp of P type transistor 22A/22B and voltage Vdsatp of tail current source transistor 20. Voltage Vdsatp is the minimum drain-source voltage of transistor 20 which will permit the transistor to operate as a current source. Again, the value of Vgsp is the sum of the threshold voltage of Vtp of the P type device and voltage Vdsatp of the transistor. Assuming that the threshold voltage of a P type device using a standard CMOS process is 900 millivolts and that voltage Vdsatp is 200 millivolts, the voltage at the inputs of the amplifier must be at least 1.3 volts below the supply voltage for the input stage to operate. Since the inputs to the amplifier (nodes A and B) must be at least 650 millivolts, the minimum power supply voltage is 1.95 volts. This minimum supply voltage value is too high for some applications.
There is a need for a band gap voltage reference circuit which can utilize a standard CMOS process and which can satisfactorily operate with a supply voltages significantly less than 2 volts. The present invention provides a band gap reference circuit that can be implemented using a standard CMOS process and which can operate at supply voltages substantially less that 2 volts. These and other advantages of the present invention will become apparent to those skilled in art from a reading of the following Detail Description of the Invention together with the drawings.
A band gap circuit is disclosed which is capable of being implemented using a standard CMOS process. The circuit includes first and second bipolar transistors, such as vertical PNP transistors, having respective bases connected together and respective collectors connected together. Current biasing circuitry is provided which is coupled to the emitters of the first and second bipolar transistors that causes the two transistors to operate at different current densities. Typically, the two transistors have differing emitter areas, with the current biasing circuitry operating to cause current flow through the two transistors to be equal so that a difference in current density is maintained.
The band gap circuit further includes voltage biasing circuitry coupled intermediate the bases and the collectors of the bipolar transistors which is configured to produce a non-zero base-collector bias voltage. Preferably, the bias voltage is on the order of 500 millivolts. The bias voltage operates to elevate the emitter voltage of the two transistors to allow the use of a differential amplifier having standard N type MOS input transistors to be used as part of the current biasing circuitry.